The present invention relates generally to improved apparatus and methods for testing electrical circuit devices, particularly integrated circuit chips and the like.
The conventional approach to testing integrated circuit chips is to employ testing apparatus which can be adapted (by programming or the like) for testing a plurality of different types of integrated circuits. In such an approach, a series of test input patterns are applied to the inputs of the chip being tested while the outputs are monitored to determine whether the proper corresponding output patterns are obtained. Such test equipment is complex and expensive, since the input and output patterns of integrated circuit chips may vary widely. Also, the time required for reprogramming the tester for each different chip slows up the testing process. In addition, where programmable chips are to be tested (such as PROMs), the particular input-output pattern may be changed many times during design and de-bugging phases.